MJ Logic Design
Layer 4 Processor

This block was part of an Application Delivery System Platform, and was
responsible for supporting L2-L7 traffic in hardware, with an emphasis on
terminating TCP connections and supporting subsequent L5-7 processing.  
The design was partitioned across two Xilinx Virtex-E 3200E FPGA devices,
contained four clock domains (25/33/66/133MHz), and managed 23 separate
memory structures (NtRAM, DDR SDRAM).  Key functions included:  
  • input context-switching with per-context state to support
    header/payload processing and subsequent packet reassembly in a
    cell-interleaved environment
  • efficient buffer management and per-flow virtual queuing (via linked
    lists) necessary to support up to 1M active TCP connections
  • L3/4 header processing
  • 4-tuple hash table look-up (DRAM-based) to determine flow binding
  • bulk of TCP termination requirements (i.e., connection setup/teardown,
    byte re-order, window management, timers, retransmit, etc)
  • multiple forwarding options to support L5-L7 processing