MJ Logic Design
Programmable Micro-Coded Engine

This block was part of a TCP Offload ASIC, and was a Very Long Instruction
Word (VLIW) microcoded engine that was tailored to perform packet
parsing/building for layers 2-4 (Ethernet/IP/TCP) as well as upper layer
protocols (e.g., ISCSI).  Key performance indicators included supporting line
rate Rx/Tx Ethernet/IP/TCP packets across a 10G SPI-4 link (one instance
each for Rx/Tx, where L2 header included VLAN/802 and TCP header
contained parsed timestamp option).  Total gate count equivalent was ~100k
plus instruction memory, and achieved timing closure at 300MHz in a 0.13
micron process.  Key functions included:  
  • programmable input field extraction of varying size, length, and offset
  • multiple 16- and 32-bit ALUs
  • general-purpose register file to drive ALUs and error-control/output
    packing logic
  • programmable packing logic to drive checksum/CRC
    checking/generation logic
  • programmable output packing that allowed headers to be generated
    and pre-pended to packet payloads (e.g., custom headers for ingress
    packets, standard L2-4 headers for egress packets)
  • SECDED-protected instruction word
  • 0-penalty if/else branching and 1-clk penalty elsif branching
  • hardware-controlled branching on SOP/EOP events