MJ Logic Design
Packet Processor ASIC

This ASIC was used on a Quad OC-48 Line Card (within a terabit router) and
performed classification/routing at 8.33MPkts/sec for IPv4, MPLS, and various
control protocols, and supported either a single OC-48 or quad OC-12
channels.  The ASIC included four internal clock domains (33/66/100/133MHz)
and implemented in 1.2M gates using LSI G11 process (Note: Final tapeout
eliminated quad OC-12 mode in order to reduce gate count).  Product shipped
first silicon.  Key functions included:  
  • Utopia 3+ Packet-Over-Sonet (POS) interface
  • programmable Layer 3/4 Protocol Decode function which extracted
    various L3/4 fields (based on programmable settings) used for
    classification/routing and various packet integrity checks
  • classification/routing cores based on third-party algorithms
  • RFC1812 Martian Address filtering
  • per-flow Input Rate Policing (GCRA-based algorithm)
  • CRC32
  • TTL/Checksum update
  • IPv4 fragmentation
  • per-flow/port statistics counters