MJ Logic Design
Traffic Services Module (TSM) Card

This card was the centralized traffic scheduling engine for an Application
Delivery System Platform. Key TSM features included:
  • Flow-based rate and response-time traffic shaping implemented using
    calendar scheduling
  • Multicast processing
  • Statistics harvesting and reporting
  • An interface to a software-based load balancing engine
  • A TCAM-based IP lookup engine

The design was partitioned across three large Xilinx Virtex-E FPGAs (one
XCV1000E and two XCV2600Es) and two smaller Virtex-E parts (XCV400E and
XCV600E). The design managed 10 data structures in separate NtRAM
memory structures, and 4 data structures in separate DDR SDRAM structures.
Additionally, the design utilized clock-forwarded DDR FPGA-to-FPGA
communication interfaces. Design flow included using Synplicity for synthesis
and the Xilinx Place & Route tools for floor-planning of the higher frequency
portions of the design.